The present invention relates to a semiconductor memory device and more particularly to a technical means to reduce a through-current flowing in the same device and a technical means to optimize the column selection timing.
As an example of a semiconductor memory device, a dynamic random access memory (hereinafter, abbreviated as “DRAM”) has been proposed. This DRAM is comprised of a plurality of dynamic memory cells which are allocated in the structure of an array. Regarding such semiconductor memory device, a technical means has been proposed to utilize a column selection signal in a write execution section and a read execution section of the semiconductor memory device wherein a column change-over switch is provided and a write control section and a read control section are respectively provided with the write execution section and the read execution section for every column (Japanese Patent Application Publication Nos. Hei 4(1992)-85793, Hei 5(1993)-258567, Hei 9(1997)-161483 (corresponding U.S. Pat. No. 5,724,291) and 2000-132969 (corresponding U.S. Pat. No. 6,359,825B1)).
Moreover, a technical means to control a read column switch and a write column switch with independent signal lines in the semiconductor memory device has also been proposed (Japanese Patent Application Publication No. Hei 5(1993)-62463).